Fault Detection in Parity Preserving Reversible Circuits
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International Symposium on Multiple-Valued Logic (ISMVL)
Motivated by its variety of applications in several(emerging) technologies, the design of reversible circuits received significant attention in the recent past. With the emergence of physical realizations, also the consideration of faults and fault-tolerance became important. It has been suggested that parity preserving circuits would be ideal for fault detection, since here the parity of the inputs is the same as the parity of the outputs.
Hence, if there is a fault on any single output, the parity should be flipped which would make the fault easy to detect. This paper however shows that this is not always the case. In fact, we provide and discuss examples showing that it is not sufficient to have parity preserving circuits when considering established fault models for reversible logic. As a result of our investigations, we can conclude that, even if a reversible circuit is parity preserving,it has to be checked against a particular fault model.