Exact Stimuli Minimization for Simulation-Based Verification
Sprache des Titels:
Englisch
Original Buchtitel:
International Symposium on circuits and Systems (IEEE)
Original Kurzfassung:
Due to the ever increasing complexity of modern
circuits and systems, verification represents one of the most
time-consuming tasks in the entire design process for embedded
systems. For this purpose, simulation-based techniques are widely
applied in industrial contexts. Here, stimuli are determined which
are used as input for the Design under Verification (DUV) and are
supposed to trigger different aspects of the new design. However,
usually much more stimuli are generated than actually needed
to comprehensively cover all aspects. This obviously increases
the run time of the verification significantly. Consequently,
verification engineers aim for minimizing the number of stimuli
after their generation ? without loosing their coverage. Existing
solutions, however, usually generate results which are far from
being optimal. Besides that, their scalability is severely limited.
In this work, we propose a solution for an exact minimization of
stimuli. To this end, we utilize the computational power of modern
reasoning engines such as MAX-SAT solvers which can efficiently
minimize a given set of stimuli. Experimental evaluations confirm
that, compared to previous work, up to 63% further reduction
can be obtained and scalability significantly increases.
Forschungs-