An Efficient Memristor Crossbar Architecture for Mapping Boolean Functions using Binary Decision Diagrams (BDD)
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The memristor is considered as the fourth fundamental circuit element along with resistor, capacitor and induc-tor. It is a two-terminal passive circuit element whose resistance value changes based on the amount of chargeflowing through it. Another property of the memristor is that its resistance change is non-volatile in nature, andhence can be used for non-volatile memory applications. Researchers have been exploring memristors from var-ious perspectives such as logic design and storage applications. In this paper, a slicing crossbar architecture forthe efficient mapping of Boolean functions is proposed which exploits gate level parallelism using the memristoraided logic (MAGIC) design style. A Boolean function is first represented as aBinary Decision Diagram(BDD).The BDD nodes are expressed as netlists of NOR and NOT gates, and are mapped to the proposed slicing crossbararchitecture with parallel node evaluation where possible. This is the first approach that combines BDD-basedsynthesis with MAGIC gate evaluation on memristor crossbar, while at the same time avoiding crossbar-relatedproblems using a slicing architecture. Experimental evaluations on standard benchmark functions show consid-erable improvement in the solutions.