Architectural Exploration of Arbitrary Sampling Rate Converters
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Arbitrary sampling rate converters are employed to convert discrete-time signals be- tween two different sampling rates with arbitrary ratios. The main focus of this work is to analyze and compare an integrator-based interpolator structure with state-of-the- art architectures like the Farrow or the Newton structure using Lagrange interpolation polynomials.
The investigated integrator-based up-sampler is a patented solution which is not-yet- published in a scientific journal. It can be employed for both interpolation and deci- mation. The fundamental idea is to use an integrator chain with resettable integrator start values in order to calculate interpolated samples with low hardware complexity, i.e. additions only, at the high output sampling rate of the interpolator. Conversely, the more complex arithmetic operations to calculate the integrator start values are shifted to the lower sampling rate. The benefit of this architecture increases with increasing interpolation ratios.
The integrator chain is defined by N integrator reset values, referred to as coefficients, for a polynomial of order N. In this thesis the calculation of these coefficients is derived for different polynomial basis functions. For each approach the number of required arith- metic operations is evaluated. The results are analyzed and summarized for the lower and the higher clock domains. Finally a selected set of strategies to derive the quantized integrator coefficients is implemented and simulated in MATLAB. The performance in terms of spectral replica suppression and interpolation error is analyzed in the frequency and the time domain, depending on different coefficient word lengths and interpolation ratios. All results are compared to state-of-the-art architectures for upsampling.
The findings of this thesis show that the bottleneck of the integrator-based interpolator is the coefficient word length which must be higher in order to achieve a similar performance as the well-known standard interpolators. However the integrator-based architecture shows clear advantage in terms of hardware cost for high arbitrary interpolation ratios and low-order interpolation polynomials. The investigations of this work prove that an interpolation ratio of 5 results in an efficient solution in terms of executed operations on the higher clock domain.