Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits
Sprache des Vortragstitels:
Englisch
Original Tagungtitel:
International Symposium on Electronic System Design (ISED)
Sprache des Tagungstitel:
Englisch
Original Kurzfassung:
Although different from the conventional computing paradigm,
reversible computation received significant interest due
to its applications in various (emerging) technologies. Here, computations can be executed not only from the inputs to the outputs,
but also in the reverse direction. This leads to significantly
different design challenges to be addressed. In this work, we
consider problems that occur when describing a reversible control
flow using
Hardware Description Languages
(HDLs). Here, the
commonly used conditional statements must, in addition to the
established
if-condition for forward computation, be provided
with an additional
fi-condition for backward computation. Unfortunately, deriving correct and consistent
fi-conditions is often
not obvious. Moreover, HDL descriptions exist which may not
be realized with a reversible control flow at all. In this work,
we propose automatic solutions which generate the required
fi-conditions and check whether a reversible control flow indeed
can be realized. The solution utilizes
predicate transformer seman-
tics based on
Hoare logic. This has exemplary been implemented for the reversible HDL
SyReC and evaluated with a variety of circuit description examples. The proposed solution constitutes
the first automatic method for these important designs steps in
the domain of reversible circuit design.
Forschungs-