Capacitive-DAC based Transmitter Architectures: Modeling and Digital Pre-Processing
Sprache des Vortragstitels:
IMS/RFIC Workshop WMB: Digital-Intensive Wireless Transmitters for 4G/5G Broadband Mobile Communications
Sprache des Tagungstitel:
The switched capacitor power amplifier (SCPA) or radio frequency (RF) capacitive digital-to-analog converter (C-DAC) combines the functionality of a mixer, a digital-to-analog converter, and a power amplifier (PA). The superior amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) linearity makes the SCPA attractive for implementations in mobile communication systems for latest communication standards such as Universal Mobile Telecommunications System (UMTS) or Long Term Evolution (LTE).
In this talk the principle idea of the C-DAC as a configurable capacitive voltage divider, which additionally performs the mixing operation in dependency of the applied LO carrier signal, will be introduced. Two different transmitter structures, the IQ C-DAC based architecture and the polar C-DAC based architecture will be discussed. The C-DAC consists of an array of switched-capacitor cells, where each cell ideally consists of a CMOS inverter and a capacitor. An ideal C-DAC is perfectly linear. However, non-ideal components, i.e. switch parasitics and variations of the capacitors in the cells, cause the C-DAC to become non-linear, and thus generate AM-AM and AM-PM distortions. In addition, imperfect power supply sources generate unwanted harmonics in the C-DAC?s RF output signal. We present a switched non-linear state space model (SSM) which allows studying these effects with significantly reduced simulation run-time compared to circuit simulators. A comparison between the non-linear SSM, a transistor-level circuit model, and measurements on a 28 nm CMOS test chip is given for single tone as well as modulated LTE test signals. Furthermore, we will discuss digital pre-distortion concepts to improve the spectral regrowth behavior and the error vector magnitude (EVM) of an IQ C-DAC based architecture. The approaches have been validated using the non-linear SSM as well as circuit level simulations, and by measurements with the 28 nm CMOS test chip.
Sprache der Kurzfassung:
Hauptvortrag / Eingeladener Vortrag auf einer Tagung