Test Pattern Generation Effort Evaluation of Reversible Circuits
Sprache des Vortragstitels:
Englisch
Original Tagungtitel:
Conference on Reversible Computation
Sprache des Tagungstitel:
Englisch
Original Kurzfassung:
The problem of synthesis and optimization of reversible and
quantum circuits have drawn the attention of researchers for more than
one decade. With physical technologies for realizing the quantum bits
(qubits) being announced, the problem of testing such circuits is also
becoming important. There have been several works for identifying fault
models for reversible circuits, and test generation algorithms for the
same. In this work, we aim to show that the problem of testing reversible
circuits with respect to recent fault models (like missing gate, missing
control, reduced control, etc.) is easy, and it is not really worth to spend
time and effort for generating better test patterns. To establish this point,
test generators using two extreme scenarios have been implemented: a
naive test generator that is very fast but does not guarantee optimality
and a SAT-based test generator that is slow but guarantees smallest
test sets. Experiments have been carried out on reversible benchmark
circuits, which establish the fact that the size of the test patterns does
not drastically differ across the spectrum.
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