A Staircase Structure for Scalable and Efficient Synthesis of Memristor-Aided Logic
Sprache des Vortragstitels:
Englisch
Original Tagungtitel:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Sprache des Tagungstitel:
Englisch
Original Kurzfassung:
The identification of the memristor as fourth fundamental circuit
element and, eventually, its fabrication in the HP labs provide new
capabilities for in-memory computing. While there already exist
sophisticated methods for realizing logic gates with memristors,
mapping them to crossbar structures (which can easily be fabricated)
still constitutes a challenging task. This is particularly the
case since several (complementary) design objectives have to be satisfied,
e.g. the design method has to be scalable, should yield designs
requiring a low number of timesteps and utilized memristors, and
a layout should result that is hardly skewed. However, all solutions
proposed thus far only focus on one of these objectives and hardly
address the other ones. Consequently, rather imperfect solutions are
generated by state-of-the-art design methods for memristor-aided
logic thus far. In this work, we propose a corresponding automatic
design solution which addresses all these design objectives at once.
To this end, a staircase structure is utilized which employs an almost
square-like layout and remains perfectly scalable while, at the
same time, keeps the number of timesteps and utilized memristors
close to the minimum. Experimental evaluations confirm that the
proposed approach indeed allows to satisfy all design objectives at
once.
Forschungs-