Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning
Sprache des Vortragstitels:
Englisch
Original Tagungtitel:
Great Lakes Symposium on VLSI (GLVLSI)
Sprache des Tagungstitel:
Englisch
Original Kurzfassung:
The complexity of todays System on Chips (SoCs) forces designers
to use higher levels of abstractions. Here, early design decisions
are conducted on abstract models while different configurations
describe how to actually realize the desired SoC. Since those decisions severely affect the final costs of the resulting SoC (in terms of utilized area, power consumption, etc.), a fast and accurate cost
estimation is essential at this design stage. Additionally, the resulting costs heavily depend on the adopted logic synthesis algorithms,
which optimize the design towards one or more cost objectives. But
how to structure a cost estimation method that supports multiple
configurations of an SoC, implemented by use of different synthesis
strategies, remains an open question. In this work, we address this
problem by providing a cost estimation method for a configurable
SoC using Machine Learning (ML). A key element of the proposed
method is a data representation which describes SoC configurations
in a way that is suited for advanced ML algorithms. Experimental
evaluations conducted within an industrial environment confirm
the accuracy as well as the efficiency of the proposed method.
Forschungs-