An Untrimmed 14-bit Non-Binary SAR-ADC Using 0.37 fF-Capacitors in 180 nm for 1.1 µW at 4 kS/s
Sprache des Vortragstitels:
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
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This paper presents a differential, fully-dynamic, and self-clocked 14-bit non-binary SAR ADC manufactured in a 180 nm CMOS process working at 1 V supply voltage while consuming 1.125 µW of power. The ADC is designed for a sampling frequency of 4096 Hz and utilizes an integrated oversampling ratio of 4 resulting in a Nyquist bandwidth of 512 Hz using an integrated low-power decimation filter to reduce the output data rate for the targeted ultra-low-power bio-signal acquisition-systems. The 14-bit capacitive DAC implements 10-bit thermometer and 4-bit binary cells and achieves an untrimmed DNL of 0.48 LSB using a 0.37 fF minimum waffle-capacitor.