Cross-Level Compliance Testing and Verification for RISC-V
Sprache des Vortragstitels:
Design and Verification Conference and Exhibition Europe (DVCon)
Sprache des Tagungstitel:
RISC-V is an open and royalty-free Instruction Set Architecture (ISA) that gained enormous momentum in both academia and industry in recent years. The major goal of the RISC-V ISA is to provide a path to a new era of processor innovation via open standard collaboration. RISC-V became a game changer for embedded systems in several application areas including e.g. IoT and Edge devices. RISC-V features an extremely modular and extensible design that provides enormous flexibility in building application specific solutions that can leverage custom extensions and only include features that are really required. However, this enormous flexibility also leads to a significantly increased risk of introducing SW incompatibilities between different RISC-V implementations, thus causing fragmentation of the RISC-V ecosystem. This very important problem is addressed with compliance testing. More precisely, compliance testing checks whether registers are missing, modes are not there, instructions are absent, as well as the presence of only those instructions which are part of the selected ISA. If the compliance test passes for a CPU, the HW/SW contract is maintained and the SW will be portable between implementations. Note that compliance testing is not design verification. In contrast to compliance testing, the goal of verification is to find errors in the CPU implementation and ultimately prove that an implementation is correct. Thus, thorough verification has to be performed later in the development phase and is complementary to compliance testing.