Programmable Analysis of RISC-V Processor Simulations using WAL
Sprache des Vortragstitels:
Design and Verification Conference and Exhibition Europe 2022
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With RISC-V?s growing traction, both researchers and companies race to bring their RISC-V implementations to the public. Here, especially RISC-V?s extensibility has created a very diverse ecosystem with RISC-V cores ranging from low power to high performance and superscalar architectures. In this diverse ecosystem, knowing the performance specifications of a RISC-V core is essential for both, designers and users when placing the core on the market or selecting a suitable RISC-V core. In this paper, we demonstrate the use of the open-source domain specific language WAL to analyze performance specifications of multiple configurations of open-source as well as a commercial RISC-V core. WAL programs analyze the cores based on waveforms generated during simulation and thus can easily be integrated
into standard development processes. The presented WAL programs are flexible and generic, and can be easily adapted to
different RISC-V cores.