Homogeneity Enforced Calibration of Stage Nonidealities for Pipelined ADCs
Sprache des Vortragstitels:
Microelectronic Systems Symposium MESS22
Sprache des Tagungstitel:
Pipelined analog-to-digital converters (ADCs) are fundamental components in a wide range of signal processing systems involving high sampling rates. In addition to high sampling rates, state-of-the-art signal processing systems require highly linear ADCs. Thus, calibration techniques were intensively investigated over the past years.
Most calibration techniques consist of two steps. Firstly, the ADC nonlinearities are identified, e.g., by feeding a known test signal into the ADC and measuring the respective output. In a second consecutive step, the identified nonlinearities are utilized to equalize the pipelined ADC. However, considering the high linearity of the ADCs, the first step is specifically challenging because the test signal generator (TSG) requires higher linearity than the ADC under test.
In this work, we propose a calibration technique, which does not rely on in-depth knowledge of the test signal. For that, a test signal is injected twice into the ADC. In the first time slot, the ADC output signal is scaled by a constant scaling factor. In the second time slot, however, the ADC input signal is scaled by the same scaling factor. Since a nonlinear ADC naturally violates the homogeneity condition, the difference between these two signals is nonzero and will be referred to as the homogeneity error in the following. Ultimately, a post-correction model is applied to equalize the pipelined ADC. The parameters of the post-correction model are identified by minimizing the squared homogeneity error with the stochastic gradient descent algorithm.
As the homogeneity error depends solely on the ADC output, the proposed calibration technique relaxes the linearity requirements of the TSG. Furthermore, the utilized estimation algorithm features low computational complexity, enabling an on-chip ADC calibration.