A 0.32-THz 6.6-dBm Single-Chain CW Transmitter Using On-Chip Antenna with 2.65% DC-to-THz Efficiency
Sprache des Vortragstitels:
2023 IEEE Radio Frequency Integrated Circuits Symposium
Sprache des Tagungstitel:
A 0.324-THz multiplier-based (×16) transmitter with an on-chip patch antenna has been implemented in a 130-nm SiGe:C BiCMOS technology with an fT/fmax of 350/450 GHz. Power management and biasing are integrated on-chip for post-silicon optimizations of output power and dc-to-THz efficiency. Each circuit block can be programmed over a serial peripheral interface for bias current. Three individually programmable low-dropout voltage regulators supply the ×8 20-to-160- GHz multiplier chain, the two-stage 160-GHz power amplifier, and the 0.32-THz frequency doubler, respectively. Measurements after optimization reveal a dc-to-THz efficiency of 2.65% with an output power of 6.6dBm and a dc power consumption of 170mW operating at 0.324 THz.